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The 74ABT821 is a buffered 10-bit wide version of the 74ABT374A.
The 74ABT821 is a 10-bit, edge-triggered register coupled to ten 3-state output buffers. The device is controlled by the clock (CP) and output enable (OE) control gates.The register is fully edge triggered.
The state of each D input, one set-up time before the LOW-to-HIGH clock transition is transferred to the corresponding output Q of the flip-flop.
The 3-state output buffers are designed to drive heavily loaded 3-state buses, MOS memories, or MOS microprocessors.
The active LOW output enable (OE) controls all ten 3-state buffers independent of the register operation. When OE is LOW, the data in the register appears at the outputs. When OE is HIGH, the outputs are in high-impedance OFF-state, which means they will neither drive nor load the bus.
- High-speed parallel registers with positive-edge triggered D-type flip-flops
- Ideal where high speed, light loading, or increased fan-in are required with MOS microprocessors
- Output capability: +64 mA and -32 mA
- Power-on 3-state
- Power-on reset
- Latch-up protection exceeds 500 mA per JESD78B class II level A
- ESD protection:
- HBM JESD22-A114F exceeds 2000 V
- MM JESD22-A115-A exceeds 200 V
To learn more about NXP 74ABT821, click on the link below:
http://www.eeweb.com/company-news/nxp/high-performance-10-bit-d-type-flip-flop/